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1/37 STW5094 november 2003 features: complete stereo audio dac and filters including: n 18 bit digital to analog converters. n linear phase digital filters. n active linear phase smoothing filter. n 30 w load stereo headphones drivers, 8 w load mono loudspeaker driver for group listening. stereo audio dac features: n multibit sd modulator with data weighted averaging dac. n 92 db dynamic range, 0.01% thd over 30 w load performance. n supports all the mpeg 1 & 2 sampling frequencies and the extension to mpeg 2.5: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 khz. n tones from tone generator can be injected in the audio paths. stereo headphones and loudspeaker/earpiece power amplifiers features and stereo input for fm radio features: n 20khz bandwidth stereo headphones outputs. driving capability: 20mw (typ. 0.1% t.h.d) over 30 w with 40 db range programmable gain. n balanced earpiece loudspeaker output. driving capability: 190mw (typ. 0.1% t.h.d) over 8 w with 30db range programmable gain. n analog stereo input for fm radio with 38 db range programmable gain. complete codec and filter system including: n 14 bit linear adc and dac. n 8 bit companded adc and dac a-law or m -law. n transmit and receive digital band-pass filters. n active antialias and smoothing filters. n 8 w load earpiece/loudspeaker driver, 30 w load auxiliary driver. voice codec features: n support both 8khz and 16khz sampling rate. n one microphone biasing output. n remote control function. n one line input and two switchable microphone amplifier inputs. 42.5db range programmable gain. n transient supression during power up and power down. n internal programmable sidetone circuit. n internal ring, tone and dtmf generator. n programmable pwm buzzer driver. general features: n single 2.7v to 3.3v supply. n extended temperature range operation (*) -40c to 85c. n 1 m w standby power (typ. at 2.7v). n 13 mw operating power in audio listening mode (typ. at 2.7v). n 11 mw operating power in voice codec mode (typ. at 2.7v). n 1.8v to 3.3v cmos compatible digital interfaces. n programmable pcm interface. n i 2 c compatible control interface. n programmable serial audio data input interface (i 2 s and other formats). (*) functionality guaranteed in the range - 40c to +85c; timing and electrical specifications are guaranteed in the range - 30c to +85c. tfbga 6x6 (36 pins) ordering number: STW5094 18 bit 8khz to 48khz low power stereo audio dac with integrated power amplifiers and voice codec
STW5094 2/37 applications: n cdma,gsm,dcs1800,pcs1900,jdc digital cellular telephones with mp3 and fm radio stereo listening functions. n portable devices with a stereo digital audio source and fm radio listening function. general description STW5094 is a low power stereo audio dac device with headphones amplifiers for high quality mp3 and fm radio listening. the STW5094 includes also an high performance low power combined pcm codec filter tailored to implement the audio front-end functions required by low voltage low power consumption digital cellular terminals with added mp3 and fm radio listening. STW5094 offers a number of programmable functions accessed through an i 2 c-bus compatible interface. the STW5094 stereo audio dac section is suited for mp3, or any other audio stereo source, listening. it supports all the mp3 rates from 8khz to 48khz. the audio data serial interface is i 2 s compatible and can be programmed to handle 16 to 24 bit word length in- put data. the internal d to a converters work with 18 bit input resolution. the stereo headphones drivers can also be used for fm radio listening via an auxiliary stereo analog in- put. a loudspeaker driver can also be used for mono- phonic group listening. the STW5094 voice codec section can be configured either as a 14-bit linear or as an 8-bit companded pcm coder. the frame synchronism frequency of the voice codec can be either the standard 8khz val- ue or the extended 16khz one. in addition to the stereo audio dac and codec filter functions, STW5094 includes a tone ring dtmf generator that can be used both in audio listening mode and in voice codec mode, a sidetone generation, a buzzer driver output and a re- mote control function tailored to handle an external on-hook off-hook button. STW5094 voice codec fulfills and exceeds d3 d4 and ccitt recommendations and etsi requirements for digital handset terminals. the stereo audio dac part fulfills and exceeds the requirements for mp3 quality and fm radio quality listening. main applica- tions include digital mobile phones, as cellular and cordless phones, with added low-power high-quality mp3 and or fm radio listening features, or any bat- tery powered equipment that requires stereo audio dac with headphones drivers operating at low single supply voltage. pin connections (top view) 23456 1 a b c d e f mic2p remout mclk dr dx mic2n mic1n mbias vcc fs gnd mic1p vcca cap2 remin auxclk lrck mic3 fmr gndcm vccio sdi sck gnda hpl gndp dnc ock bz fml lsp vccp hpr sda scl lsn tfbga 6x6x1.2 (36 pin)
3/37 STW5094 functional block diagram note: this diagram shows the functionality of the device and of some register bits but it does not necessarily reflect the exac t hardware implementation fm mode voice mode audio mode audio mode voice mode voice mode ock sck sdi lrck remin remout dr dx fs mclk sda scl hpr fmr hpl lsn lsp fml mic1p mic1n mic2p mic2n mic3 bz mbias cap2 rte se on power reset rte se fme right driver fmr preamp left driver bandgap vcm registers diff driver fml preamp sd modulator interpolation filter control logic analog filter sd modulator interpolation filter dac rx channel filter i 2 s i/f pcm i/f remocon i 2 c i/f tx channel filter adc tone att. tone generator anti alias filter buzzer mic. bias voice preamp 0/20db gain. si de gndp gndcm vcca gnda vccp vcc gnd vccio sidetone gain fme analog filter analog filter dac dac aux ck auxclk gen os os suppression transient filter suppression transient filter mute mute suppression transient filter +18:-20 db step 2 +18:-20 db step 2 0:-40 db 0:-40 db +6:-24 db 0:22.5 db 0:-27 db -12:-27 db
STW5094 4/37 pin function pin n name type description b1 mic1p ai positive high impedance input to transmit preamplifier for microphone 1 connection. b2 mic1n ai negative high impedance input to transmit preamplifier for microphone 1 connection. a2 mic2p ai positive high impedance input to transmit preamplifier for microphone 2 connection. a1 mic2n ai negative high impedance input to transmit preamplifier for microphone 2 connection. c1 mic3 ai high impedance single ended input to transmit preamplifier for line input connection. only 0db gain is allowed. b3 mbias ao microphone biasing switch. e1 fml ai auxiliary analog audio left channel input. d2 fmr ai auxiliary analog audio right channel input. f2,f1 lsp, lsn ao receive analog amplifier complementary outputs. this differential output can drive 50nf (with series resistor) or directly an earpiece transductor of 8 w . the signal at this output can be: the sum of the receive speech signal from dr, the internal tone generator, and the sidetone signal, or the sum of the audio left channel and the internal tone generator, or can come from fml input. e2 hpl ao audio headphone amplifier left channel output. this output can drive 50nf (with series resistor) or directly an earpiece transductor of 30 w . the signal at this output can be the sum of audio left channel and internal tone generator, or the sum of receive speech signal from dr, internal tone generator, sidetone signal, or can come from fml input. f4 hpr ao audio headphone amplifier right channel output. this output can drive 50nf (with series resistor) or directly an earpiece transductor of 30 w . the signal at this output can be the sum of audio right channel and internal tone generator, or the sum of receive speech signal from dr, internal tone generator, sidetone signal, or can come from fmr input. a3 remout do remocon function digital output. c4 remin di remocon function input. a high level at this pin is detected as a non pressed key, while a low level is detected as a pressed key. e6 bz ao pulse width modulated buzzer driver output. f6 scl di i2c-bus interface serial clock input. scl is asynchronous with the other system clocks. f5 sda dio i2c-bus interface serial data input-output. c6 lrck di left right clock for audio interface input. d6 sck di audio interface clock input. d5 sdi di audio interface data input. e5 ock di master clock input for audio mode. can also be used as master clock in tone only and fm modes. a6 dx dot transmit data output: data is shifted out on this pin during the assigned transmit time slots. elsewhere dx output is in the high impedance state. in delayed and non-delayed normal frame sync modes, voice data byte is shifted out from tristate output dx at the mclk frequency on the rising edge of mclk, while in non-delayed reverse frame sync mode voice data is shifted out on the falling edge of mclk. a5 dr di receive data input: data is shifted in during the assigned received time slots in delayed and non-delayed normal frame sync modes voice data byte is shifted in at the mclk frequency on the falling edges of mclk, while in non-delayed reverse frame sync mode voice data byte is shifted in on the rising edge of mclk.
5/37 STW5094 type definitions : ai - analog input, ao - analog output, di - digital input, do - digital output, dot - digital output tristate, dio - digital input output open drain, p - power supply or ground. b5 fs di frame sync input: this signal is a 8 16khz clock which defines the start of the transmit and receive frames. any of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. a4 mclk di master clock input for voice mode. can also be used as master clock in tone only and fm modes. the allowed clock frequencies are 512 khz, 1.536 mhz, 2.048 mhz or 2.56 mhz. mclk is the voice data clock. c5 auxclk di auxiliary clock input. can be used as master clock in tone only and fm modes. allowed clock frequencies are 512khz, 1.536mhz, 2.048mhz or 2.56mhz. e4 dnc ai do not connect. this pin must be left unconnected. c3 cap2 ai a capacitor must be connected between this node and ground. c2 vcca p power supply input for the analog section. vcc and vcca can be directly connected together for low cost applications. d1 gnda p analog ground: all analog signals are referenced to this pin. gnd and gnda can be connected together for low cost applications. f3 vccp p power supply input for the output drivers. vccp and vcca must be connected together. e3 gndp p power ground. output drivers are referenced to this pin. gndp and gnda must be connected together. d3 gndcm p analog ground connection. gndcm can be connected to gnda. b4 vcc p power supply input for the digital section. b6 gnd p ground for the digital section d4 vccio p power supply input for the digital i o pins. pin n name type description pin function (continued)
STW5094 6/37 functional description i device modes STW5094 can work in 4 different modes, selected by bits md in control register 18 ( cr18 ). depending on the mode different data interfaces, clock inputs, and internal blocks are selected. a built-in power consumption management function keeps in power down the blocks that are not needed by the selected operating mode. in all the modes the output drivers can be activated in all the combinations allowed by bits os in cr6 (in case of stereo input and lsp n driver selected the left channel is sent to this driver, while in case of voice input and hpl + hpr drivers selected the same signal is sent to both drivers). i.1 audio mode: in audio mode the path from the i 2 s i f to the output drivers is active to allow the stereo audio dac function. the i 2 s i f is active while the pcm i f is inactive. the master clock of the device is ock . the ock frequency must be 256 times the sampling frequency for the mpeg1 and mpeg2 sampling frequencies and 512 times for the mpeg2.5 sampling frequencies. the sampling frequency ( lrck frequency) can be selected with bits lay and afs in reg6 . since the ock clock is used directly in all the audio blocks, its jitter and spectral properties must be adequate to the desired audio quality. the tone ring dtmf generator can be activated if needed. the fm preamplifiers are in power down. i.2 voice mode: in voice mode the tx path from microphone or line input to dx and the rx path from dr to the output drivers are active to allow the pcm codec function. the pcm i f is active while the i 2 s i f is inactive. the master clock of the device is mclk , the frequency of the clock can be selected with bits f in cr0 . the fm preamplifiers are in power down. i.3 tone only mode: in tone only mode the path from the tone generator to the output drivers and to the buzzer is active to allow tones or ringer listening only. both i 2 s i f and pcm i f are inactive, as all the audio and voice converters functions. the master clock of the device can be selected to be auxclk , mclk or ock (bits cfm in cr18 ). the tone ring dtmf generator can be activated if needed. the fm preamplifiers are in power down. i.4 fm mode: in fm mode the path from fml and fmr analog inputs to the output drivers is active to allow fm stereo radio listening. both i 2 s i f and pcm i f are inactive, as all the audio and voice converters functions. the master clock of the device can be selected to be auxclk , mclk or ock (bits cfm in cr18) . the tone ring dtmf generator is in power down. ii device operation ii.1 power on initialization and software reset: when power is first applied, power on reset circuitry initializes STW5094 and puts it into the power down state. all the registers are initialized as indicated in the control register description section. all the functions are disabled. the registers can be initialized also writing bit srs (software reset) in cr18.
7/37 STW5094 ii.2 power up down control: it is recommended that all programmable functions (excluding the gain controls) are set while the device is powered down. power state control can then be included in the last programming instruction (the power up bit pu is located in the last address register ( cr18 ) so that the multi-byte mode of the control interface can be easily used to program all the required functions before power up). when a power up command is given, all the circuits needed for the selected mode are activated (in voice mode the dx output will remain in the high impedance state until the second fs pulse after power up arrives). a built-in power consumption management function keeps in power down the blocks that are not needed by the selected operating mode. ii.3 power down state: following a period of activity, power down state may be reentered by writing 0 in bit pu in cr18 . all the control registers remain in their current state and can be changed by i 2 c control interface. in addition to the power down instruction, the detection of absence of the current master clock (no transition detected) automatically puts the device in power down state without setting bit pu . if transitions on the master clock are detected the device is put again in power up. ii.4 voice transmit section: this section is active in voice mode. voice transmit analog preamplifier gain is designed in two stages to enable gains up to 42.5 db. stage 1 provides a selectable 0 or 20 db gain via bit pg in cr4 . stage 2 is a programmable gain amplifier which provides from 0 to 22.5 db of additional gain in 1.5db step. it can be programmed with bits txa in cr4 . two differential microphone inputs ( mic1p n, mic2p n ) and one single ended line input ( mic3 ) are provided. the line input mic3 can only be used with preamplifier gain set to 0db in both stages. the microphone input or transmit mute is selected with bits ms in cr4 . in the mute case, the analog transmit signal is grounded. a separate mbias output can be used to bias a microphone (bit mb in cr4 ). an active anti-alias filter then precedes the single bit sd analog to digital converter that is followed by an 8th order iir digital tx channel filter. the tx channel filter is band-pass if the fs frequency is 8khz and low-pass if the fs frequency is 16khz (bit vfs in cr0 ). a precision on chip voltage reference ensures accurate and highly stable transmission levels. any offset voltage arising in the analog blocks is cancelled by an internal autozero circuit. voice data is sent to the pcm i f to be serially sent to dx output. ii.5 voice receive section: this section is active in voice mode. voice data coming from pcm i f dr pin is sent to the 8th order digital iir rx channel filter. the filter can be selected to be band-pass or low-pass, with bit hpb in cr5 , when fs frequency is 8khz, while it is always low-pass when fs frequency is 16khz. the filter is followed by a sd digital to analog converter and a 3rd order switched-capacitor reconstruction filter. the sidetone can be summed to the received signal (bit si in cr5 ) and its amplitude can be programmed with bits sa in cr5 . ii.6 stereo audio dac section: this section is active in audio mode. the left and right audio samples coming from the i 2 s interface are interpolated with an fir filter in order to feed the oversampled multi-bit sd modulator, the digital to analog converter is followed by a 3rd order switched-capacitor reconstruction filter. ii.7 output drivers section: there are 3 analog output drivers. the lsp n differential driver delivers 190mw typical power with 0.1% t.h.d. (140mw minimum undistorted) on a 8 w earpiece loudspeaker (piezoceramic loads up to 50nf can also be driven, with a series resistor), it has a 30db range gain control (bits lsa in cr7 ). the 2 single ended drivers ( hpl and hpr ) deliver 20mw typical power with 0.1% t.h.d. (16.5mw minimum undistorted) on 30 w stereo headphones, they have a 40db range gain control ( cr8 for hpl and cr9 for hpr ). it is possible to put all the drivers in power-down, enable the lsp n one, enable the hpl one or enable hpl and hpr together
STW5094 8/37 programming bits os in cr6 . these settings are not dependent from the selected operative mode. if hpl and hpr are enabled together in voice mode or tone only mode the same signal is sent to both drivers. the active drivers can be muted (keeping them in power-up state) using bit mut in cr7 . at power-up or after a change in os bits the outputs are muted for 10 ms to avoid unwanted noise. the transient suppression filter is used to avoid clicks when the gain value is changed. ii.8 tone generator: the tone generator can be activated (writing cr12 ) in all the STW5094 operating modes except fm mode. in voice and audio modes the tones are summed to the signal. it is possible to generate 1 or 2 summed waveforms (either sinusoidal or square wave), their frequencies can be set in cr13 for the first one (f1) and in cr14 for the second one (f2) accordingly to the values listed in table 1. the amplitude of the generated waveform can be regulated in cr12 over a 33db range. when both f1 and f2 are selected the amplitude of f1 and f2 are lowered by 5db and 7db respectively with respect to the amplitude of a single waveform. in this way the amplitude of the summed waveforms does not overload and there is a 2db difference between f1 and f2 amplitude as required for dtmf generation. the tone generator output can be sent to the voice transmit section (in voice mode), to the power amplifiers, possibly mixed with audio or voice, (in all the modes except fm mode) and to the buzzer output bz (in all the modes except fm mode). ii.9 buzzer output: the output bz is intended to drive a buzzer, via an external bjt, with a squarewave pulse width modulated (pwm) signal. the frequency of the signal is stored in cr13 (see table1 for frequency values). for some applications it is also possible to multiply this pwm signal with a squarewave signal having a frequency stored in cr14 . the duty cycle of the buzzer output can be varied in cr15 in order to change the buzzer volume. maximum load for bz is 5k w and 50pf. ii.10 voice data interface (pcm i f): the pcm i f is used to exchange the voice data in both tx and rx direction, it can be programmed for linear format data or companded a-law or m -law format (see fig.1, 2 and 3). frame sync input fs determines the beginning of frame. it may have any duration from a single cycle of mclk to a squarewave. three different relationships may be established between the frame sync input and the first time slot of the frame by setting bits dm in cr1 . in non delayed normal and reverse data mode (long frame timing) the first time slot starts at the rising edge of fs. in delayed data mode (short frame sync timing) fs input must be high for at least a half cycle of mclk before the frame start. when linear code is selected (bit cm =0 in cr0 ) the msb is transmitted and received first, the word length is 16 bit. when companded code is selected (bit cm =1 in cr0 ) a time slot assignment may be used in all timing modes (bit ts in cr1 ), that allows connection to one of the two b1 and b2 voice data channels. two data formats are available: in format 1, time slot b1 corresponds to the 8 mclk cycles that immediately follow the rising edge of fs , while time slot b2 corresponds to the 8 mclk cycles that immediately follow time slot b1. in format 2, time slot b1 is identical to format 1 while time slot b2 appears two bit slots after time slot b1. this two bits space is left available for insertion of the d channel data. data format is selected by bit ff in cr0 . bit en in cr1 enables or disables data transfer on dx and dr . outside the selected time slot dx is in the high impedance condition. during the selected time slot the dx output and the dr input are synchronized as follow: -if delayed or non-delayed modes are selected the transmit voice data is sent to dx output on the rising edges of mclk and receive voice data is read at dr input on the falling edges of mclk . -if non-delayed reverse mode is selected the transmit voice data register is sent to dx output on the falling edges of mclk and receive voice data is read at dr input on the rising edges of mclk. when 16khz frame sync frequency is selected (bit vfs in cr0 ) the rx and tx filters are both low-pass and their cutoff frequencies are doubled. it is possible to access the b channel data when companded a-law or m -law formats are used (bits mx and mr in cr1 ). a byte written into cr3 will be sent to dx output in place of the transmit channel pcm data. a byte written in cr2 will be sent to the receive path. the current byte received on dr input can be read in cr2 .
9/37 STW5094 ii.11 audio data interface (i 2 s i f): the i 2 s i f is used to receive the left and right channel audio data (see fig. 4 and 5). the interface is i 2 s compatible and can be configured in other different modes writing cr16 . when the i 2 s i f is active (audio mode) the master clock of the device is ock . the frequency of ock is 256 times the sampling frequency ( lrck frequency) when the sampling frequency is between 16khz and 48khz ( lay(1) =0 in cr6 ), and 512 times when the sampling frequency is between 8khz and 12khz ( lay = 10 in cr6 ). the polarity of ock can be selected . sck frequency is 32 times the lrck one in case of 16bit data word and 64 times in case of 18bit to 24bit data word. left channel data are always received first, the polarity of lrck can be selected. the first 35 data frames after power up are discarded while the interpolation filters data memory is cleared. ii.12 control interface (i 2 c i f): the i 2 c i f is used to program the device by writing and reading the control registers (see fig 6 and 7). the interface is i 2 c bus compatible, being the STW5094 a slave device. sda is the bidirectional open-drain data pin and scl is the input clock pin. the device address is e2 hex. for writing and e3 hex. for reading. the interface has an internal address register that keeps the current address of the control register to be read or written. at each write access of the interface the address register is loaded with the data of the register address field. the value in the address register is increased after each data byte read or write. it is possible to access the interface in 2 modes: single-byte mode in which the address and data of a single register are specified, and multi-byte mode in which the address of the first register to be written or read is specified and all the following bytes exchanged are the data of successive address registers starting from the one specified (in multi-byte mode the internal address counter restart from register 0 after the last register 18). using the multi-byte mode it is possible to write or read all the registers with a single access to the device on the i 2 c bus. the control interface can be used both in power-up and power-down state. ii.13 master clock in fm mode and tone only modes: in fm mode and in tone only mode the master clock of the device can be selected to be auxclk , mclk or ock writing bits cfm in cr18 . the auxiliary clock auxclk can be used when the audio mode clock ock and the voice mode clock mclk are not available. auxclk and mclk frequency selection is done with bits f in cr0 . ii.14 remocon function: the remocon (remote control) function can be used to detect the status of an headset button. the remocon function is enabled by setting bit ren in cr17 . if enabled, this function is active also when the STW5094 is in power-down state. a high level at remin input is detected as a non pressed button, while a low level is detected as a pressed button. the "pressed button" information can be treated in 2 ways depending on bit rlm in cr17 : - if rlm = 0 (transparent mode) the information at remin is seen at remout after a debounce time of 50ms maximum; - if rlm = 1 (latched mode) the information stored in bit rdl in cr17 is seen at remout . rdl is set after a debounce time of 50ms maximum when a low level at remin is detected. rdl is reset with power on initialization and can also be reset writing 0 in bit rdl . the remout output polarity can be inverted setting bit roi in cr17 : the pressed button information is presented at remout output as a logic 1 if bit roi = 0. if roi = 1 the polarity is inverted.
STW5094 10/37 iii programmable registers control register cr0 functions (address: 0x00) (1): significant in companded mode only *: state at power on initialization control register cr1 functions (address: 0x01) (1) significant in companded mode only *: state at power on initialization x: reserved: write 0 76543210 function f(1:0) vfs cm ma ia ff b7 0 0 1 1 0 1 0 1 mclk or auxclk = 512 khz mclk or auxclk = 1.536 mhz mclk or auxclk = 2.048 mhz mclk or auxclk = 2.560 mhz * 0 1 voice data fs is 8 khz * voice data fs is 16 khz 0 1 linear code * companded code linear code companded code 0 0 1 1 0 1 0 1 2-complement * sign and magnitude 2-complement 1-complement m -law: ccitt d3-d4 * m -law: bare coding a-law including even bit inversion a-law: bare coding 0 1 b1 and b2 consecutive (1) * b1 and b2 separated (1) 0 1 8 bits time-slot (1) * 7 bits time-slot (1) 76543210 function dm(1:0) mr mx en ts dl 0 1 1 x 0 1 delayed data timing * non-delayed normal data timing non-delayed reverse data timing x 0 1 d r connected to rx path * cr2 connected to rx path (1) 0 1 tx path connected to d x * cr3 connected to d x (1) 0 1 pcm i/f disabled * pcm i/f enabled 0 1 b1 channel selected * b2 channel selected (1) 0 1 normal operation * digital loopback
11/37 STW5094 control register cr2 functions (address: 0x02) (1) significant in companded mode only. control register cr3 functions (address: 0x03) (1) significant in companded mode only. control register cr4 functions (address: 0x04) *: state at power on initialization (1) when the single ended line input mic3 is selected, microphone gain must be set to 0db (pg=1, txa=0000). control register cr5 functions (address: 0x05) *: state at power on initialization x: reserved: write 0 (1): valid only when voice data fs=8khz (vfs=0). when voice data fs=16khz (vfs=1) the high pass filter is always disabled. 76543210 function drd(7:0) msb lsb data sent to receive path or data received from dr input (1) 76543210 function dxd(7:0) msb lsb dx data transmitted (1) 76543210 function ms(1:0) mb pg txa(3:0) 0 0 1 1 0 1 0 1 transmit input muted * mic1 selected mic2 selected mic3 selected (1) 0 1 mbias output disabled * mbias output enabled 0 1 20db preamplifier gain * 0db preamplifier gain (1) 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db transmit amplifier gain (1)* 1.5 db transmit amplifier gain transmit amplifier in 1.5 db step 22.5 db transmit amplifier gain 76543210 function hpb si sa(3:0) xx 0 1 voice codec receive high pass filter enabled (1) * voice codec receive high pass filter disabled 0 1 voice codec internal sidetone disabled * voice codec internal sidetone enabled 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 -12.5 db sidetone gain * -13.5 db sidetone gain sidetone gain in 1 db step -27.5 db sidetone gain
STW5094 12/37 control register cr6 functions (address: 0x06) (1): ock frequency must be 256 times audio data fs frequency. (2): ock frequency must be 512 times audio data fs frequency. *: state at power on initialization x: reserved: write 0 control register cr7 functions (address: 0x07) *: state at power on initialization x: reserved: write 0 control register cr8 functions (address: 0x08) *: state at power on initialization x: reserved: write 0 76543210 function lay(1:0) afs(1:0) os(1:0) se rte 0 0 1 0 1 x audio data fs is 32 or 44.1 or 48 khz (1) * audio data fs is 16 or 22.025 or 24 khz. (1) audio data fs is 8 or 11.025 or 12 khz. (2) 0 0 1 0 1 x audio data fs is 44.1 or 22.05 or 11.025 khz * audio data fs is 48 or 24 or 12 khz. audio data fs is 32 or 16 or 8 khz. 0 0 1 1 0 1 0 1 output drivers off * lsp n output driver selected. hpl output driver selected. hpl and hpr output drivers selected. 0 1 audio or voice codec signal to ls or hp disabled * audio or voice codec signal to ls or hp enabled. 0 1 ring tone to ls or hp disabled * ring tone to ls or hp enabled. 76543210 function mut lsa(3:0) xxx 0 1 the selected output drivers are operative * the selected output drivers are muted 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 earpiece loudspeaker amplifier 6 db gain * earpiece loudspeaker amplifier 4 db gain earpiece loudspeaker amplifier gain in 2 db step earpiece loudspeaker amplifier -24 db gain 76543210 function hpla(4:0) xxx 0 0 - 1 0 0 - 0 0 0 - 1 0 0 - 0 0 1 - 0 headphones amplifier (left channel) 0 db gain * headphones amplifier (left channel) -2 db gain headphones amplifier (left channel) gain in 2 db step headphones amplifier (left channel) -40 db gain
13/37 STW5094 control register cr9 functions (address: 0x09) *: state at power on initialization x: write 0 control register cr10 functions (address: 0x0a) *: state at power on initialization x: reserved: write 0 control register cr11 functions (address: 0x0b) *: state at power on initialization x: reserved: write 0 76543210 function hpra(4:0) xxx 0 0 - 1 0 0 - 0 0 0 - 1 0 0 - 0 0 1 - 0 headphones amplifier (right channel) 0 db gain * headphones amplifier (right channel) -2 db gain headphones amplifier (right channel) gain in 2 db step headphones amplifier (right channel) -40 db gain 76543210 function fmla(4:0) xxx 0 0 - 1 0 0 - 0 0 0 - 0 0 0 - 1 0 1 - 1 fm preamplifier (left channel) +18 db gain * fm preamplifier (left channel) +16 db gain fm preamplifier (left channel) gain in 2 db step fm preamplifier (left channel) -20 db gain 76543210 function fmra(4:0) xxx 0 0 - 1 0 0 - 0 0 0 - 0 0 0 - 1 0 1 - 1 fm preamplifier (right channel) +18 db gain * fm preamplifier (right channel) +16 db gain fm preamplifier (right channel) gain in 2 db step fm preamplifier (right channel) -20 db gain
STW5094 14/37 control register cr12 functions (address: 0x0c) *: state at power on initialization x: reserved write 0 control register cr13 functions (address: 0x0d) control register cr14 functions (address: 0x0e) control register cr15 functions (address: 0x0f) * state at power on initialization 76543210 fu nction toneg(3:0) fsel(1:0) sn de 0 0 - 1 0 0 - 0 0 0 - 1 0 1 - 1 tone gain is 0 db * tone gain is -3 db tone gain in 3 db step tone gain is -33 db 0 0 1 1 0 1 0 1 f1 and f2 muted * f1 selected f2 selected f1 and f2 in summed mode 0 1 squarewave signal selected * sinewave signal selected 0 1 to n e ring generator not connected to transmit path * to n e ring generator connected to transmit path 76543210 function f1(7:0) msb lsb binary equivalent of the decimal number used to calculate f1 see table 1 76543210 function f2(7:0) msb lsb binary equivalent of the decimal number used to calculate f2 see table 1 76543210 function be bi bz(5:0) 0 1 buzzer output disabled (set to 0) * buzzer output enabled 0 1 duty cycle is intended as the relative width of logic 1 * duty cycle is intended as the relative width of logic 0 msb lsb binary equivalent of the decimal number used to calculate the duty cycle, using the formula: dutycycle = bz(5:0) x 0.78125 %
15/37 STW5094 control register cr16 functions (address: 0x10) (1) significant in 18 20 24 bit per word mode only (2) left channel data is always received first. (3) first bit delay, in 18 20 24 bit per word mode, is applied only if word is left justified. *: state at power on initialization control register cr17 functions (address: 0x11) *: state at power on initialization x: reserved write 0 76543210 function pol ord dif inv for scl prec(1:0) 0 1 ock polarity, sck changes on the rising edge of ock * ock polarity, sck changes on the falling edge of ock 0 1 audio i/f data order, the msb is received first (i 2 s) * audio i/f data order, the lsb is received first 0 1 audio i/f data alignment, the word is left justified (i 2 s)(1) * audio i/f data alignment, the word is right justified (1) 0 1 lrck polarity, when lrck=0 left data is received (i 2 s) (2) * lrck polarity, when lrck=1 left data is received (2) 0 1 audio i/f format, i 2 s format (first bit is delayed) (3) * audio i/f format, non delayed formats 0 1 sck polarity, sdi and lrck sampled on the rising edge (i 2 s) * sck polarity, sdi and lrck sampled on the falling edge 0 0 1 1 0 1 0 1 audio i/f data width 16 bit (32 sck clocks per frame) * audio i/f data width 18 bit (64 sck clocks per frame) audio i/f data width 20 bit (64 sck clocks per frame) audio i/f data width 24 bit (64 sck clocks per frame) 76543210 function ren rlm roi rdl 0 1 remocon function disabled * remocon function enabled 0 1 remocon output in transparent mode * remocon output in latched mode 0 1 remocon output not inverted * remocon output inverted 0 1 remocon detection latch reset by m p* remocon detection latch set by internal logic xxxx
STW5094 16/37 control register cr18 functions (address: 0x12) *: state at power on initialization x: reserved write 0 76 5 4 3210 function md(1:0) cfm(1:0) srs pu 0 0 1 1 0 1 0 1 voice mode * audio mode. tone only mode. fm mode. 0 0 1 0 1 x the master clock input for tone only and fm mode is auxclk * the master clock input for tone only and fm mode is mclk the master clock input for tone only and fm mode is ock x x 0 1 normal operation * software reset, all registers are set to their default. 0 1 device is in power down * device is in power up
17/37 STW5094 table 1. tone generator frequency versus cr13 cr14 register value correspondence table cr13/14 value (dec.) f1/f2 tone frequency (hz) cr13/14 value (dec.) f1/f2 tone frequency (hz) cr13/14 value (dec.) f1/f2 tone frequency (hz) cr13/14 value (dec.) f1/f2 tone frequency (hz) 0 0.0 64 250.0 128 750.0 192 1750.0 1 3.9 65 257.8 129 765.6 193 1781.2 2 7.8 66 265.6 130 781.2 194 1812.5 3 11.7 67 273.4 131 796.9 195 1843.8 4 15.6 68 281.2 132 812.5 196 1875.0 5 19.5 69 289.1 133 828.1 197 1906.2 6 23.4 70 296.9 134 843.8 198 1937.5 7 27.3 71 304.7 135 859.4 199 1968.8 8 31.2 72 312.5 136 875.0 200 2000.0 9 35.2 73 320.3 137 890.6 201 2031.2 10 39.1 74 328.1 138 906.2 202 2062.5 11 43.0 75 335.9 139 921.9 203 2093.8 12 46.9 76 343.8 140 937.5 204 2125.0 13 50.8 77 351.6 141 953.1 205 2156.2 14 54.7 78 359.4 142 968.8 206 2187.5 15 58.6 79 367.2 143 984.4 207 2218.8 16 62.5 80 375.0 144 1000.0 208 2250.0 17 66.4 81 382.8 145 1015.6 209 2281.2 18 70.3 82 390.6 146 1031.2 210 2312.5 19 74.2 83 398.4 147 1046.9 211 2343.8 20 78.1 84 406.2 148 1062.5 212 2375.0 21 82.0 85 414.1 149 1078.1 213 2406.2 22 85.9 86 421.9 150 1093.8 214 2437.5 23 89.8 87 429.7 151 1109.4 215 2468.8 24 93.8 88 437.5 152 1125.0 216 2500.0 25 97.7 89 445.3 153 1140.6 217 2531.2 26 101.6 90 453.1 154 1156.2 218 2562.5 27 105.5 91 460.9 155 1171.9 219 2593.8 28 109.4 92 468.8 156 1187.5 220 2625.0 29 113.3 93 476.6 157 1203.1 221 2656.2 30 117.2 94 484.4 158 1218.8 222 2687.5 31 121.1 95 492.2 159 1234.4 223 2718.8 32 125.0 96 500.0 160 1250.0 224 2750.0 33 128.9 97 507.8 161 1265.6 225 2781.2 34 132.8 98 515.6 162 1281.2 226 2812.5 35 136.7 99 523.4 163 1296.9 227 2843.8 36 140.6 100 531.2 164 1312.5 228 2875.0 37 144.5 101 539.1 165 1328.1 229 2906.2 38 148.4 102 546.9 166 1343.8 230 2937.5 39 152.3 103 554.7 167 1359.4 231 2968.8 40 156.2 104 562.5 168 1375.0 232 3000.0 41 160.2 105 570.3 169 1390.6 233 3031.2 42 164.1 106 578.1 170 1406.2 234 3062.5 43 168.0 107 585.9 171 1421.9 235 3093.8 44 171.9 108 593.8 172 1437.5 236 3125.0 45 175.8 109 601.6 173 1453.1 237 3156.2 46 179.7 110 609.4 174 1468.8 238 3187.5 47 183.6 111 617.2 175 1484.4 239 3218.8 48 187.5 112 625.0 176 1500.0 240 3250.0 49 191.4 113 632.8 177 1515.6 241 3281.2 50 195.3 114 640.6 178 1531.2 242 3312.5 51 199.2 115 648.4 179 1546.9 243 3343.8 52 203.1 116 656.2 180 1562.5 244 3375.0 53 207.0 117 664.1 181 1578.1 245 3406.2 54 210.9 118 671.9 182 1593.8 246 3437.5 55 214.8 119 679.7 183 1609.4 247 3468.8 56 218.8 120 687.5 184 1625.0 248 3500.0 57 222.7 121 695.3 185 1640.6 249 3531.2 58 226.6 122 703.1 186 1656.2 250 3562.5 59 230.5 123 710.9 187 1671.9 251 3593.8 60 234.4 124 718.8 188 1687.5 252 3625.0 61 238.3 125 726.6 189 1703.1 253 3656.2 62 242.2 126 734.4 190 1718.8 254 3687.5 63 246.1 127 742.2 191 1734.4 255 3718.8
STW5094 18/37 timing diagram figure 1. voice interface (pcm i/f) non delayed data timing mode (*) figure 2. voice interface (pcm i/f) delayed data timing mode (*) (*) in the case of companded code the timing is applied to 8 bits instead of 16 bits. t dmz t sfm t hmf t hmf t wlm t wmh t rm t fm t dmd t dfd t sdm t hmd 1 1 2 3 4 5 6 7 16 2 3 4 5 6 7 16 3 2 1 4 5 6 7 16 17 mclk fs dx dr t hmf t sfm t dmz t sfm t wlm t wmh t rm t fm t dmd t sdm t hmd 1 1 2 3 4 5 6 7 16 2 3 4 5 6 7 16 3 2 1 4 5 6 7 16 17 mclk fs dx dr
19/37 STW5094 timing diagram figure 3. voice interface (pcm i/f) non delayed reverse data timing mode (*) (*) in the case of companded code the timing is applied to 8 bits instead of 16 bits. figure 4. audio interface (i 2 s i/f) timing t dmzr t sfmr t hmfr t hmfr t wlm t wmh t rm t fm t dmdr t dfd t sdm t hmd 1 1 2 3 4 5 6 7 16 2 3 4 5 6 7 16 3 2 1 4 5 6 7 16 17 mclk fs dx dr ock ock sck sdi lrck (polarity inverted) t dai t hock t lock
STW5094 20/37 figure 5. audio interface (i 2 s i/f) formats lrck sck sdi 16 1 2 13 14 15 16 1 2 13 14 15 16 left channel right channel msb lsb msb lsb i 2 s format (delayed), data word 16 bit, msb first (default) lrck sck sdi x 1 2 17 18 x 1 2 left channel right channel i 2 s format (delayed), data word 18 bit, left justified, lsb first x lsb msb lsb 16 sck 17 18 x x msb 32 sck lrck sck sdi 1 2 3 23 24 x 2 3 left channel right channel non-delayed format, data word 24 bit, left justified, msb first, lrck polarity inverted 1 msb lsb msb 23 24 x 1 lsb 32 sck lrck sck sdi 1 2 3 14 15 16 1 2 3 14 15 16 1 left channel right channel non-delayed format, sck polarity inverted, data word 16 bit, lsb first 16 sck msb msb lsb lsb for the other possible formats see control register cr16 description lrck sck sdi x 18 left channel right channel data word 18 bit, right justified, msb first x msb x 1 2 x lsb 32 sck 18 x x msb x 1 2 lsb 32 sck 32 sck 32 sck 16 sck 16 sck
21/37 STW5094 figure 6. control interface (i 2 c i/f) formats figure 7. control interface (i 2 c i/f) timing figure 8. a.c. testing input, output waveform write single byte start device address reg n address reg n data in ack ack ack stop write multi byte start device address reg n address reg n data in ack ack ack stop reg n+m data in ack m+1 data bytes current addr start device address current reg data out ack no ack stop read single byte current addr start device address current reg data out ack no ack stop read multi byte curr reg+m data out ack ack ack m+1 data bytes start device address reg n address ack ack start device address reg n data out 111000 11 ack no ack stop random addr read single byte random addr read multi byte start device address reg n address ack ack start device address 111000 11 no ack stop reg n+m data out ack ack m+1 data bytes reg n data out ack 11100011 11100011 11100010 11100010 11100010 11100010 (sto) t su (sta) t su (sta) t hd (dat) t su t high t buf (dat) t hd t f t r t low (sta) t hd p s p s r scl sda p = stop s = start sr = start repeated ac testing: inputs are driven at 0.8vccio for a logic "1" and 0.2vccio for a logic "0". timing measurements are made at 0.7vccio for a logic "1" and 0.3vccio for a logic "0". test points 0.7v ccio 0.3v ccio 0.7v ccio 0.3v ccio 0.8v ccio 0.2v ccio input output
STW5094 22/37 absolute maximum ratings operative supply voltages timing specifications (unless otherwise specified, v ccio = 1.8v to 3.3v,t amb = -30c to 85c; typical characteristics are specified at v ccio =3.0v, t amb = 25 c; all signals are referenced to gnd, see next note for timing definitions) notice: all timing specifications subject to change. ock and audio interface signals timing mclk and auxclk timing parameter value unit v cc to gnd 4.6 v voltage at mic (v cc 3.3v) v cc +0.5 to gnd -0.5 v current at lsp/n 240 ma current at hpr,hpl 100 ma current at any digital output 50 ma voltage at any digital input (v ccio 3.3v); limited at 50ma v ccio + 0.5 to gnd -0.5 v storage temperature range - 65 to + 150 c symbol min. max. unit v cc =v cca =v ccp 2.7 3.3 v v ccio 1.8 v cc v symbol parameter test condition min. typ. max. unit f ock frequency of ock (frequency depends on the selected audio sample rate in cr6 ) audio fs 8khz or 16khz audio fs 11.025khz or 22.05khz audio fs 12khz or 24khz audio fs 32khz audio fs 44.1khz audio fs 48khz 4.096 5.6648 6.144 8.192 11.2896 12.288 mhz mhz mhz mhz mhz mhz t hock period of ock high measured from v ih to v ih 35 ns t lock period of ock low measured from v il to v il 35 ns t dai delay of sck,sdi and lrck from ock active edge 020ns symbol parameter test condition min. typ. max. unit f mclk frequency of mclk, auxclk frequency is programmable with bits f in cr0 512 1.536 2.048 2.560 khz mhz mhz mhz t wmh period of mclk, auxclk high measured from v ih to v ih 150 ns t wml period of mclk, auxclk low measured from v il to v il 150 ns t rm rise time of mclk, auxclk measured from v il to v ih 30 ns t fm fall time of mclk, auxclk measured from v ih to v il 30 ns
23/37 STW5094 pcm interface timing i 2 c bus control port timing note: a signal is valid if it is above vih or below vil and invalid if it is between vil and vih.for the purpose of this specificatio n the following conditions apply (see fig. 8): a) all input signal are defined as: vil = 0.2vccio, vih = 0.8vccio, tr < 10ns, tf < 10ns. b) delay times are measured from the inputs signal valid to the output signal valid. c) setup times are measured from the data input valid to the clock input invalid. d) hold times are measured from the clock signal valid to the data input invalid. symbol parameter test condition min. typ. max. unit t hmf hold time mclk low to fs low 10 ns t sfm setup time, fs high to mclk low 30 ns t dmd delay time, mclk high to data valid load = 20pf 100 ns t dmz delay time, mclk low to dx disabled 10 100 ns t dfd delay time, fs high to data valid load = 20pf; applies only if fs rises later than mclk rising edge in non delayed mode only 100 ns t sdm setup time, dr valid to mclk receive edge 20 ns t hmd hold time, mclk low to dr invalid 10 ns t hmfr hold time mclk high to fs low 30 ns t sfmr setup time, fs high to mclk high 30 ns t dmdr delay time, mclk low to data valid load = 20pf 100 ns t dmzr delay time, mclk high to dx disabled 10 100 ns t hmdr hold time, mclk high to dr invalid 20 ns symbol parameter test condition min. typ. max. unit f scl clock frequency 400 khz t high clock high time 600 ns t low clock low time 1300 ns t r sda and scl rise time 1000 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time 600 ns t su:sta start condition setup time 600 ns t hd:dat data input hold time 0 ns t su:dat data input setup time 250 ns t su:sto stop condition setup time 600 ns t buf bus free time 1300 ns
STW5094 24/37 electrical characteristics (unless otherwise specified, v ccio = 1.8v to 3.3v, t amb = -30c to 85c; typical characteristic are specified at v ccio = 3.0v, t amb = 25c; all signals are referenced to gnd) digital interfaces (see figure 8) analog interfaces * with series resistor symbol parameter test condition min. typ. max. unit v il input low voltage all digital inputs except remin dc ac 0.3v ccio 0.2v ccio v v v ih input high voltage all digital inputs except remin dc ac 0.7 vccio 0.8 vccio v v v ilrem input low voltage remin input 0.5 v v ihrem input high voltage remin input 1.4 v v ol output low voltage all digital outputs, i l =10 m a all digital outputs, i l = 2ma 0.1 0.4 v v v oh output high voltage all digital outputs, il = 10 m a all digital outputs, il = 2ma v ccio -0.1 v ccio -0.4 v v i il input low current any digital input, gnd < v in < v il -10 10 m a i ih input high current any digital input, v ih < v in < v ccio -10 10 m a i oz output current in high impedance (tristate) dx and co -10 10 m a symbol parameter test condition min. typ. max. unit r mbias mbias output resistance mbias 100mv under v cc 150 w i mic mic input leakage gnd < v mic < v cc -100 +100 m a r mic mic input resistance gnd < v mic < v cc 50 k w r fm fm input resistance fml, fmr to cap2 30 k w r lhp single ended drivers load resistance hpl, hpr to gndp 30 w c lhp single ended drivers load capacitance hpl, hpr to gndp 100 50* pf nf r ovhp single ended drivers output resistance steady zero pcm code applied to dr; i = 1ma 1 w r lls differential driver load resistance lsp to lsn 8 w c lls differential driver load capacitance lsp to lsn 100 50* pf nf r ols differential driver output resistance steady zero pcm code applied to dr; i = 1ma 1 w v osls differential offset voltage at lsp, lsn alternating zero pcm code applied to dr maximum receive gain; r l =50 w -50 +50 mv
25/37 STW5094 analog input/output operative ranges microphone input levels - absolute levels at mic1, mic2 line input level - absolute levels at mic3 fm input levels - absolute levels at fml, fmr power output levels - absolute levels at hpl, hpr power output levels - absolute levels at lsp-lsn (differentially measured) tones levels note: when 2 tones are enabled the amplitude of f1 is lowered by 5db and the amplitude of f2 is lowered by 7db with respect to the amplitude of a single tone. symbol parameter test condition min. typ. max. unit 0 dbm0 level transmit gain 0db 493 mv rms overload level transmit gain 0db 707 2 mv rms v pp 0 dbm0 level transmit gain 20db 49 mv rms overload level transmit gain 20db 71 200 mv rms mv pp 0 dbm0 level transmit gain 42.5db 3.7 mv rms overload level transmit gain 42.5db 5.3 15 mv rms mv pp symbol parameter test condition min. typ. max. unit overload level transmit gain 0db 354 1 mv rms v pp symbol parameter test condition min. typ. max. unit overload level fml, fmr gain 18 db 177 0.5 mv rms v pp overload level fml, fmr gain from 6 to -20db 707 2 mv rms v pp symbol parameter test condition min. typ. max. unit maximum undistorted level 30 w load 707 2 mv rms v pp symbol parameter test condition min. typ. max. unit 0 dbm0 level ls gain 0db 984 mv rms 0 dbm0 level ls gain -24db 62.1 mv rms maximum undistorted level 8 w load 1.06 3 v rms v pp symbol parameter test condition min. typ. max. unit tone level at lsp-lsn single tone, sinusoidal waveform, t one gain 0db, ls gain 0db 1.41 4 v rms v pp tone level at hpl, hpr single tone, sinusoidal waveform, tone gain 0db, hpl, hpr gain -6db 707 2 mv rms v pp tone level at dx voice mode, single tone, sinusoidal waveform, tone gain 0db -1.64 dbfs
STW5094 26/37 voice codec characteristics (unless otherwise specified, v cc = 2.7v to 3.3v, t amb = -30c to 85c; fs frequency = 8khz; typical characteristics are specified at v cc = 3.0v, t amb = 25c, mic1 2 = 0dbm0, dr = -6dbm0 pcm code, f = 1015.625 hz; all signal are referenced to gnd) amplitude response transmit path (*) the limit at frequencies between 4600hz and 8000hz lies on a straight line connecting the two frequencies on a linear (db) scale versus log (hz) scale. symbol parameter test condition min. typ. max. unit g xa transmit gain absolute accuracy transmit gain programmed for minimum. measure deviation of digital pcm code from ideal 0db m0 pcm code at dx -0.5 0.5 db g xag transmit gain variation with programmed gain measure transmit gain over the range from maximum to minimum setting. calculate the deviation from the programmed gain relative to gxa, i.e. g axg =g actual - g prog. - g xa -0.5 0.5 db g xat transmit gain variation with temperature measured relative to g xa . min. gain < g x < max. gain -0.1 0.1 db g xav transmit gain variation with supply measured relative to g xa g x = minimum gain -0.1 0.1 db g xaf8 transmit gain variation with frequency. fs frequency = 8khz (vfs=0) digital filter characteristics f = 60 hz f = 100 hz f = 200 hz f = 300 hz f = 400 hz to 3000 hz f = 3400 hz f = 4000 hz f = 4600 hz (*) f = 8000 hz (*) -1.5 -0.5 -1.5 -30 -20 -6 0.5 0.5 0.0 -14 -35 -47 db db db db db db db db db g xaf16 transmit gain variation with frequency. fs frequency = 16khz (vfs=1) digital filter characteristics f = 100 hz f = 200 hz to 6000 hz f = 6800 hz f = 8000 hz f = 9200 hz (*) f = 16000 hz (*) -1.5 -0.5 -1.5 0.5 0.5 0.0 -14 -35 -47 db db db db db db g xal transmit gain variation with signal level sinusoidal test method. reference level = -10 dbm0 v mic = -40 dbm0 to +3 dbm0 v mic = -50 dbm0 to -40 dbm0 v mic = -55 dbm0 to -50 dbm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 db db db
27/37 STW5094 amplitude response (continued) receive path symbol parameter test condition min. typ. max. unit g rahpl g rahpr g rals receive gain absolute accuracy receive gain programmed for maximum apply -6 dbm0 pcm code to dr measure hpl, hpr, lsp-lsn -0.5 0.5 db g raghpl g raghpr g ragls receive gain variation with programmed gain measure hpl, hpr, lsp-lsn gain over the range from maximum to minimum setting. calculate the deviation from the programmed gain relative to g ra , i.e. g ragls =g actual - g prog . - g rals -0.5 0.5 db g rat receive gain variation with temperature measured relative to gra. (hpl, hpr and lsp-lsn) min. gain < g r < max. gain -0.1 0.1 db g rav receive gain variation with supply measured relative to gra. (hpl, hpr and lsp-lsn) g r = maximum gain -0.1 0.1 db g raf8 receive gain variation with frequency (hpl, hpr and lsp-lsn) fs frequency = 8khz ( vfs=0) . high pass filter enabled (hpb = 0). digital filter characteristics f = 60hz f = 100hz f = 200 hz f = 300 hz f = 400 hz to 3000 hz f = 3400 hz f = 4000 hz -1.5 -0.5 -1.5 -20 -12 -2 0.5 0.5 0.0 -14 db db db db db db db receive gain variation with frequency (hpl, hpr and lsp-lsn) fs frequency = 8khz ( vfs=0) . high pass filter disabled (hpb = 1). digital filter characteristics f = 50hz f = 100 hz to 3000 hz f = 3400 hz f = 4000 hz -1.5 -0.5 -1.5 0.5 0.5 0.0 -14 db db db db g raf16 receive gain variation with frequency (hpl, hpr and lsp-lsn) fs frequency = 16khz ( vfs=1) . digital filter characteristics f = 100hz f = 200 hz to 6000 hz f = 6800 hz f = 8000 hz -1.5 -0.5 -1.5 0.5 0.5 0.0 -14 db db db db g ralhpl g ralhpr g ralls receive gain variation with signal level (hpl, hpr and lsp-lsn) sinusoidal test method reference level = -10 dbm0 dr = -40 dbm0 to -3 dbm0 dr = -50 dbm0 to -40 dbm0 dr = -55 dbm0 to -50 dbm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 db db db
STW5094 28/37 envelope delay distortion with frequency noise crosstalk symbol parameter test condition min. typ. max. unit dxa tx delay, absolute f = 1600 hz 320 m s dxr tx delay, relative f = 500 - 600 hz f = 600 - 800 hz f = 800 - 1000 hz f = 1000 - 1600 hz f = 1600 - 2600 hz f = 2600 - 2800 hz f = 2800 - 3000 hz 290 180 50 20 55 80 180 m s m s m s m s m s m s m s dra rx delay, absolute f = 1600 hz 280 m s drr rx delay, relative f = 500 - 600 hz f = 600 - 800 hz f = 800 - 1000 hz f = 1000 - 1600 hz f = 1600 - 2600 hz f = 2600 - 2800 hz f = 2800 - 3000 hz 200 110 50 20 65 100 220 m s m s m s m s m s m s m s symbol parameter test condition min. typ. max. unit nxp tx noise, p weighted (up to 35db) v mic = 0v, de = 0 -75 -70 dbm0p nrp rx noise, c-message weighted 8 w load (gain for max. undistorted output level) receive pcm code = zero, si = 0, rte = 0 and lsa=0100 (gain -2db) 30 50 m v rms psrtx psrr, tx mic = 0v, v cc = 3.0 v dc + 50 mv rms ; f = 100hz to 50khz 30 db psrrx psrr, rx pcm code equals positive zero, v cc = 3.0v dc + 50 mv rms f = 100 hz - 4 khz f = 4 khz - 50 khz 30 30 db db sos spurious out-band signal at the output digital filter characteristics 4600 hz - 5600 hz 5600 hz - 7600 hz 7600 hz - 8400 hz -40 -50 -50 db db db symbol parameter test condition min. typ. max. unit ct x-r transmit to receive transmit level = 0 dbm0, f = 300 - 3400 hz dr = quiet pcm code -100 -65 db ct r-x receive to transmit receive level = -6 dbm0, f = 300 - 3400 hz mic = 0v -80 -65 db
29/37 STW5094 distortion receive path (*) the limit curve shall be determined by straight lines joining successive coordinates given in the table. symbol parameter test condition min. typ. max. unit s tdrls (*) signal to total distortion (lsp-lsn) (up to 14db attenuation) 8 w load typical values are measured with 14db attenuation. sinusoidal test method (measured using linear 300 hz to 3400 hz weighting, fs=8khz) level = +3 dbm0 level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 65 62 54 44 34 29 19 77 70 67 59 49 39 34 24 db db db db db db db db signal to total distortion (lsp-lsn) (up to 14db attenuation) 8 w load typical values are measured with 14db attenuation. sinusoidal test method (measured using linear 300 hz to 6800 hz weighting, fs=16khz) level = +3 dbm0 level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 74 67 64 56 46 36 31 21 db db db db db db db db signal to total distortion (hpl, hpr) (up to 14db attenuation) typical values are measured with 14db attenuation sinusoidal test method (measured using linear 300 hz to 3400 hz weighting, fs=8khz) level = +3 dbm0 level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 74 67 64 56 46 36 31 21 db db db db db db db signal to total distortion (hpl, hpr) (up to 14db attenuation) typical values are measured with 14db attenuation sinusoidal test method (measured using linear 300 hz to 6800 hz weighting, fs=16khz) level = +3 dbm0 level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 71 64 61 53 43 33 28 17 db db db db db db db
STW5094 30/37 distortion transmit path (*) the limit curve shall be determined by straight lines joining successive coordinates given in the table. symbol parameter test condition min. typ. max. unit s tdx (*) signal to total distortion (up to 35db gain) fs frequency = 8khz. typical values are measured with 30.5db gain sinusoidal test method (measured using linear 300 hz to 3400 hz weighting) fss = 0 level = +3 dbm0 level = 0 dbm0 level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 68 64 59 49 40 30 25 15 75 73 68 64 54 44 34 29 19 db db db db db db db db db signal to total distortion fs frequency = 16khz. typical values are measured with 30.5db gain sinusoidal test method (measured using linear 300 hz to 6800 hz weighting) fss = 1 level = +3 dbm0 level = 0 dbm0 level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 72 70 65 61 51 41 31 26 16 db db db db db db db db db
31/37 STW5094 stereo audio dac and fm characteristics (unless otherwise specified, v cc = 2.7v to 3.3v, t amb = -30c to 85c; typical characteristics are specified at v cc =3v, t amb = 25c; ock = 12.288mhz; full-scale input sine waves, 1015.625hz; input sample rate (fs) = 48khz; input data = 18bits; sck = 3.072 mhz; measurement bandwidth is 20hz to 20khz, unweighted. resistive load on hpl, hpr = 30 w ) (*) valid for i 2 s input (audio mode). note: fs range: 8khz - 48khz. symbol parameter test condition min. typ. max. unit n resolution (*) 18 bits dynr dynamic range a-weighted 89 92 db thdl total harmonic distortion maximum load 2v pp output hpl, hpr gain set to -6db 30 w load 0.01 0.03 % thd total harmonic distortion 2v pp output hpl, hpr gain set to -6db 1k w load 0.004 % deviation from linear phase (*) measurement bandwidth 20hz to 20khz, fs= 48khz.combined digital and analog filter characteristics. 1 f pb passband (*) combined digital and analog filter characteristics. 0 0.45fs khz passband ripple (*) combined digital and analog filter characteristics. 0.2 db f sb stopband (*) combined digital and analog filter characteristics. 0.55fs khz stopband attenuation (*) combined digital and analog filter characteristics. measurement bandwidth up to 3.45fs 50 db tsf transient suppression filter cutoff frequency 20 hz out of band noise measurement bandwidth 20khz to 100khz. zero input signal -90 dbr t gd group delay (*) 0.4 ms interchannel isolation (*) hpr, hpl unloaded 100 db interchannel gain mismatch 0.2 db gain error 0.5 db sut startup time from power up 11 ms
STW5094 32/37 power dissipation ( unless otherwise specified, v cc = 2.7v to 3.3v, t amb = -30c to 85c, lsp, lsn and hpl, hpr outputs not loaded; typical characteristics are specified at v cc =3v, t amb = 25c) symbol parameter test condition min. typ. max. unit i cc0 power down current, remocon off sda, scl= v ccio -0.1v remocon function disabled (ren = 0) 0.4 m a i cc0r power down current, remocon on sda, scl= v ccio -0.1v remocon function enabled (ren = 1) remin = v ilrem or remin = v ihrem 2 m a i cc1 power up current in voice codec mode fs=8khz. lsp/n output selected 4 6 ma i cc2 power up current in stereo audio mode fs=48khz. hpl,hpr outputs selected 58ma i cc3 power up current in fm stereo mode hpl,hpr outputs selected 2 3 ma
33/37 STW5094 typical performance characteristics figure 1. stereo dac performance fft audio mode (8192 points). full scale input/output sinewave at 1 khz (+3dbr) vcc=2.7v, fs=48khz, 18 bits input word. figure 2. stereo dac performance dynamic range: noise + thd [dbr] versus signal amplitude [dbm0] vcc=2.7v, fs=48khz, 18 bits input word. figure 3. voice rx performance s/(n+thd) [db] versus signal amplitude [dbm0] with 8 w output load vcc=2.7v, fs=8khz figure 4. voice tx performance s/(n+thd) versus signal amplitude vcc=2.7v, fs=8khz figure 5. digital audio filter characteristic frequency response up to 3.45 fs -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 0.5 1 1.5 2 2.5 3 amplitude [db] normalized freq. [fs] digital audio filter figure 6. digital audio filter characteristic in band frequency response -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 amplitude [db] normalized freq. [fs] digital audio filter
STW5094 34/37 typical performance characteristics (cont.) figure 7. digital rx voice filter characteristic frequency response up to 2.5fs (fs=8khz) -70 -60 -50 -40 -30 -20 -10 0 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 amplitude [db] freq. [hz] digital rx voice filter figure 8. digital rx voice filter characteristic in band frequency response (fs=8khz). -1 -0.5 0 0.5 1 0 500 1000 1500 2000 2500 3000 3500 amplitude [db] freq. [hz] digital rx voice filter figure 9. digital rx voice filter characteristic in band frequency response (fs=8khz). high pass filter disabled (hpb=1). -1 -0.5 0 0.5 1 0 500 1000 1500 2000 2500 3000 3500 amplitude [db] freq. [hz] digital rx voice filter (no high pass filt.) figure 10. tx voice filter characteristic full tx path frequency response (fs=8khz).
35/37 STW5094 application note 100k w 30 w min. bc546 bc556 100k w 1k w 33k w sckt oclk lrckt sdo dx dr mclk fs sck ock lrck sdi auxclk bz sda scl remout 100nf vccio gnd vcc gndcm vccp gndp 100nf gnda 8 w min. lsp lsn 0.47 m f fmr 0.47 m f fml 10 m f cap2 hpr hpl 150 m f 150 m f 1.5k w 3k w 10 m f vdd remin 100nf mic3 100nf mic2n 100nf mic2p mic1n 10 m f 1.8k w 750 w 100nf 100nf 750 w 1.8k w mic1p mbias sda r l line in (from fm stereo decoder) vcca vdd 10 m f 100nf 100nf vdd vddio scl i 2 c bus pcm interface auxiliary clock to microprocessor vdd buzzer 32 w i 2 s bus STW5094 sta015 mp3 decoder call/answer button electret electret line input
STW5094 36/37 outline and mechanical data tfbga36 dim. mm inch min. typ. max. min. typ. max. a 1.01 1.20 0.040 0.047 a1 0.21 0.008 a2 0.82 0.032 b 0.35 0.40 0.45 0.014 0.016 0.018 d 5.85 6.00 6.15 0.23 0.236 0.242 d1 4.00 0.157 e 5.85 6.00 6.15 0.23 0.236 0.242 e1 4.00 0.157 e 0.72 0.80 0.88 0.028 0.031 0.035 f 0.85 1.00 1.15 0.033 0.039 0.045 ddd 0.10 0.004 tfbga36 fine pitch ball grid array 7225043 body: 6 x 6 x 1.2mm
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 37/37 STW5094

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